The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs each having smaller and more complex circuits. In the course of evaluation, the geometry size or technology node (e.g., smallest component or line that can be imaged) has decreased and the number of layers making up the device has increased.
Interconnect structures of semiconductor devices connect the various active devices and circuits of the devices to a plurality of conductive pads on the external surface of the die. Multi-level interconnect structures have been developed that accommodate the advances in active-device density by routing conductive paths between the devices and the pads on the die. Multi-level interconnect structures arrange the metallization lines in multiple layers, which may be electrically isolated by surrounding dielectric material. Any number of interconnect levels may be used; typically five or more or more individual interconnect levels of conductive paths are provided to accommodate the active-device density. The conductive paths of the multi-level interconnect structures terminate in bond pads at the surface of the substrate. The bond pads are relatively large metal areas distributed about the device. Bond pads are used to establish electrical contact between the devices of the substrate and an external point such as a package substrate or a probe pin (e.g., for wafer acceptance testing).
The present disclosure relates to a method for forming a pad structure on a substrate.